Boundary-Scan Boundary Scan Technology
ICT tester requires that each node has at least one circuit test points. But with the increased device integration, and more powerful, smaller and smaller packaging, SMT components increased, the use of multilayer, PCB board component density increases, each node to put in a probe change very difficult, to increase the test point, so that manufacturing costs increase; also a powerful device for the development of a test library becomes difficult to extend the development cycle. To this end, the Joint Test Group (JTAG) testing standards promulgated IEEE1149.1. IEEE1149.1 defines a scanning device to several important features. First, define the composition of the test access port (TAP) for 4 (5] pins: TDI, TDO, TCK, TMS, (TRST). Test mode selection (TMS) is used to load the control information; second defined by the TAP control supports several different test patterns, mainly outside the test (EXTEST), to test (INTEST), run the test (RUNTEST); concludes with a boundary scan language (Boundary Scan Description Language), BSDL language to describe the scanning device is important information It defines pin as input, output and bi-directional type, defines the TAP model and instruction set with a boundary-scan device for each pin and a serial shift register (SSR) of the cell phase, called scanning unit, scanning unit together constitute a shift register chain, the pins used to control and detect its particular four pins are used to complete the test tasks would be more than one scan chain scan devices connected through their TAP together to form a continuous boundary register chain, the head of the chain plus the TAP signals can control and inspection of all connected devices with the chain pin, so that instead of a virtual contact with the needle bed fixture of the device's physical contact with each pin, virtual visit instead of the actual physical access, remove the PCB board space occupied by a large number of test pads, reducing the PCB and fixture manufacturing costs as a testing strategy, in the PCB board design for test, you can use specialized software analysis of the circuit network and a scanning device to determine how to effectively put a limited number of test points, and do not reduce test coverage, the most economical to reduce the test points and test pins. Boundary Scan technology to solve the difficulties of test points can not be increased more importantly, it provides a quick and easy way to generate test patterns, the use of software tools can convert the test pattern BSDL files, such as Teradyne's Victory, GenRad's Basic Scan and Scan Path Finder. resolved to write complex test library problems. TAP access port can be used to achieve such CPLD, FPGA, Flash Memroy online programming (In-System Program or the On Board Program).
Nand-Tree is the Inter invented a design for testability techniques. In our products, are found only within the 82371 chip design. Describe the design of the structure of a general process *. TR2 file, we can convert this file into a test vector. ICT test to be accurate fault location, testing, stability, circuit and PCB design with a great relationship. In principle, we require that every point has a network circuit test points. Circuit design to achieve the status of each device isolation, may affect each other. Of boundary scan, Nand-Tree is designed to be installed testability requirements. Edit this paragraph ICT state machine
ICT (Invite Client (Outgoing) Transaction) is a state machine to handle SIP INVITE client transaction state machine. Its like there NICT (Non-Invite Client (outgoing) Transaction) state machine, IST (Invite Server (incoming) Transaction) state machine, NIST (Non-Invite Server (incoming) Transaction) state machine, respectively, for processing SIP The non-INVITE client transaction, INVITE server transaction, non-INVITE server transaction.
ICT state machine
ICT state machine shown at left. Description: cb_ict_Nxx_received: where N is the number of values ??about 3 - cb_ict_3xx_received 4 - cb_ict_4xx_received 5 - cb_ict_5xx_received 6 - cb_ict_6xx_received