1. FPGA and PCB co-design solution:
We know that function in FPGA \ must be developed after the development of the corresponding function \ to the circuit board. In order to reduce the PCB design is often winding, pin swap and the signal pin and the FPGA can be reconfigured with each other and spend a lot of duplication of work. In the end to how to reduce development costs, reduce design time and processes?
Using Altium Designer's integrated development environment for FPGA and PCB design and simultaneous integration. Allow engineers from FPGA design, embedded processor development, line drawing, PCB production and related circuit design simulation (SPICE / SI), can be made at Altium Designer's development platform to complete. Engineers do not have to spend a lot of time learning to use multiple EDA tools Oh!
(2) develop FPGA with Altium Designer features:
Hybrid FPGA design platform
Altium Designer's FPGA design features added \ to, supports VHDL, Verilog or schematic design of FPGA, or even a mixture of C-language design, you can select your favorite way to complete your FPGA design function \ can, of course, also joined embedded software design, select Processor Softcore, build FPGA-based SOC, in the writing and execution of your software programs.
3. Free to substitute a different FPGA vendor sub-board chip:
FPGA design with the function to \ be, Altium released the function \ be strong NanoBoard development platform with complete hardware device interface allows you to more easily and quickly verify the results of FPGA design, and is not limited to any supplier of FPGA devices, makes your FPGA design project to be highly portable device, such as different vendors Actel, Altera, Lattice or Xilinx and other FPGA chips.
4. FPGA and PCB projects interactive
FPGA chips must ultimately complete the PCB layout design, FPGA with a design feature is the ability to change the allocation of IO pins in the PCB layout process can take advantage of this feature to perform FPGA pin swapping of power \ capacity, to reduce PCB layout of the staggered network, reducing the chance of winding in order to achieve optimal routing. For layout in the Designer, the changes to the FPGA chip pin immediately after a fast and easy way to change the pin state after the update to the FPGA design project.